Universal SRAM Test System Based on NI PXI Solutions

Country – Russia

Integrated circuits are being tested in different stages of manufacturing and utilization. Manufacturers conduct various tests to validate the design and verify the quality of the product. Consumers, who use ICs in their products, conduct incoming control tests to ensure the use of fault-free parts in their systems. The test of memory ICs sets some specific requirements, such as the duration of the test, in addition to the most common requirements such as cost and reliability.

Our turnkey solution is a low-cost test system that supports asynchronous SRAM ICs in almost all available packages. It runs functional and parametric tests, measures a set of electrical parameters, and delivers comprehensive results within less than five minutes of the test duration. Users can easily expand the system by adding digital I/O modules and adapter boards and increasing the number of digital channels to support high-pin-count ICs. The software allows full configuration of test steps, algorithms, and test conditions.

The system comprises the NI PXI hardware platform, custom developed adapter boards, and the software. the platform includes 200 MHz digital waveform generator/analyzer modules, which feature a per pin parametric measurement unit. The tester has four configurations that support two, four, six, and eight digital modules. The largest configuration of the system provides up to 192 digital channels.

The custom hardware implements functions of digital line multiplexing, which makes it possible to connect a power line or digital line to any pin of the IC. The socket adapter boards support a wide temperature range, from -55O ˚C to +80O ˚C, so we can test the memory ICs in a temperature chamber.

The comprehensive software has separate sections where users can create IC profiles, assign functionality of each IC pin, or create custom timing profiles to validate the functionality in boundary conditions. The test creation part empowers users to configure the sequence of various stages, which include parametric test stages or functional test stages. The system includes well-known algorithms for the memory test — Checkerboard, MATS, MARCH C-, and more. Users can create their own tests, making custom data arrays that can be written and read from the memory. Users can also conduct functional tests for the whole memory, or only in the predefined sections, providing required addresses.

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