Serial Wire Debug (SWD) is an alternative to JTAG transport method to perform operations on on–chip Debug Access Port (DAP) and peripheral specific Access Ports (AP). SWD uses an ARM standard bi-directional wire protocol, defined in the ARM Debug Interface v5, to pass data to and from the debugger and the target system in a highly efficient and standard way. It provides the interface to debug and trace functionality on processor cores and System on Chip devices, especially those that conform to the CoreSight debug and trace architecture.
Although the Serial Wire Debug protocol is not compatible directly with JTAG, it can be used to connect to legacy JTAG devices, giving additional benefits over a direct, daisy-chained JTAG architecture.
SWD Toolkit for LabVIEW easily implements and integrates Serial Wire Debug protocol in custom applications. The toolkit provides a LabVIEW FPGA Library containing drivers for SWD Master and Slave devices. Library also includes example VIs for the representation of the toolkit VIs’ usage.
Main Features of the toolkit are:
Simple API for fast integration into custom codes
Seamless integration into LabVIEW FPGA
Configurable transmission rate
Parity bit calculation on FPGA
Compatibility with LabVIEW 2018 and later
Master and Slave VIs
Examples for the representation of toolkit VIs’ usage
