- Order number: SW10007
SDLC Toolkit for LabVIEW easily implements and integrates Synchronous Data Link Control (SDLC) data communication protocol (developed by IBM) in custom applications. SDLC is equivalent to layer 2 of the Open Systems Interconnection (OSI) model of network communication.
Main Features of the toolkit are:
- Separate SDLC Transmitter and Receiver LabVIEW FPGA VIs
- Supported data rate range from 110 Baud to 10 MBaud
- Configurable baud rate
- CRC calculation on the FPGA
- Bit stuffing and unstuffing on the FPGA
- Configurable Clock Edge Mode
The toolkit provides a LabVIEW FPGA Driver Library containing two FPGA VIs, the SDLC TX (transmitter) and the SDLC RX (receiver), for data transmission and reception. Single or multichannel data communication can be implemented with additional drivers, as well as both VIs implement bit stuffing, unstuffing, CRC calculation, and forward error correction to eliminate the need for additional data processing.
The toolkit is suggested in three versions – without line encoding, with line encoding and decoding with standard, NRZ and NRZI encoding methods, as well as with clock recovery support.
The toolkit supports wide data rate range from 110 Baud to 10 MBaud. SDLC TX FPGA VI transmits data with given Baud Rate which is user-configurable. The VI contains Single Cycle Timed Loop, generates clock according to the given Baud Rate, and includes also Host to Target DMA FIFO for data transmission from Host to Target. SDLC RX FPGA VI receives SDLC data with user-configured clock edge mode (rising/falling edge), contains Single Cycle Timed Loop, and includes also Target to Host DMA FIFO for data transmission and separate Target to Host DMA FIFO for transmission of Frame size.
SDLC Toolkit version comparison.
| Feature | Versions | |||
| Standard | NRZ/NRZI encoding | Clock Recovery | NRZI Ext. TX Clock |
|
| Configurable Baud rate (110 – 10M) | + | + | + | + |
| CRC calculation on FPGA | + | + | + | + |
| Bit stuffing/unstuffing on FPGA | + | + | + | + |
| Standard line encoding | + | + | + | + |
| NRZ/NRZI line encoding | + | + | + | |
| External clock line support | + | + | ||
| Embedded clock recovery | + | + | ||
| Transmitter Clock | Internal | Internal | Internal | External |
|
NI PXIe FlexRIO Modules |
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NI PXIe-7962R NI FlexRIO FPGA Module |
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NI PXIe-7965R NI FlexRIO FPGA Module |
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NI PXIe-7966R NI FlexRIO FPGA Module |
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NI PXIe-7971R NI FlexRIO FPGA Module |
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NI PXIe-7972R NI FlexRIO FPGA Module |
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NI PXIe-7975R NI FlexRIO FPGA Module |
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NI PXIe-7976R NI FlexRIO FPGA Module |
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NI PXI FlexRIO Modules |
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NI PXI-7952R NI FlexRIO FPGA Module |
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NI PXI-7953R NI FlexRIO FPGA Module |
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NI PXI-7954R NI FlexRIO FPGA Module |
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Serial Adapter Modules for FlexRIO |
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NI 6584 (RS-422/RS 485) Adapter Module |
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NI CompactRIO Modules |
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NI-9753 C Series Differential Digital I/O Module |
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RS-9009 SDLC/HDLC and ARCNET Interface Module |
